As a CPU Verification Engineer, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation IBM Power Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Electronics / Micro Electronics / Computer Science with strong programming skills is required.
Your Role and Responsibilities:
As a CPU Verification Engineer, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems.
Key Duties:
Verification Environment Ownership: Take charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes.
Documentation and Communication: Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered. Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in IBM Server Processors.