Validation Lead

Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs.  He will be the key interface on processor Bringup Activities and own key debugs of architecture and micro-architecture  issues during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams.  Candidate must drive  coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. Candidate must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is pregerred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. 

This position requires interaction and fulfilling the requirements of IBM's Hardware Bring-up/TEST teams, Silicon Debug and understanding SPQL (Shipped Product Quality Level) requirements.