OUR STORY
At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today.
When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world!
Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.
YOUR ROLE
Responsibilities include :
• Verification planning, architecture definition, Verification test bench development and implementation at sub-system and SoC level. Extract verification matrix for regression test suits.
• Development of verification test suit and its components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs
• Development of direct and constrained-random stimulus; Understanding and analysis of RTL code, functional, assertion coverage results;
• Gate level simulations (unit delay, and with SDF annotated) and its debugging.
• Test pattern debugging and testing for verification and automatic testers.
• Strong skills in debug, failure re-creation and root cause analysis.
• Understanding of Assertion based verification or working experience on formal verification (IFV, Jasper) will be a plus
YOUR SKILLS & EXPERIENCES
• Qualification: Bachelors/Masters in Electronics/Computer Science
• AMBA, ACE, AXI bus protocols, NoC Verification.
• VHDL/Verilog/System Verilog. C- Language
• OVM/UVM, Class based verification methodologies
• Working knowledge on Multi-core processor based subsystem/SoC verification
• Communication Protocols like CAN, LIN, I2C, SPI, FlexRay.
• High Speed peripherals experience on either of Ethernet, USB, PCie or DDR. Exposure to low power simulation, safety verification will be preferred.
• Scripting proficiency - PERL, Python, UNIX/LINUX
• Simulation tools like – Xcelium/VCS/Questasim. Planning and regression tools like VManager. Experience on any of the defect and version management tools.
Work Experience - 6 - 12 years
Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future!
To discover more, visit st.com/careers
